This invention relates to a data processing system having a memory means and a counter means interconnected in a cross coupled fashion, each responsive to the output of the other.
2. Prior Art
Conventional data processing systems include memory which provides a data output responsive to an address output generated by a program counter, wherein the counter is responsive to micro control signals under micro program control. While this structure is compatible with standard data processing systems architecture, it is a limiting factor in flexibility of data processing system architecture interaction between the output of the memory and the counter.